Delay locked loop circuitry typically provides clock deskew functionality in computer processing environments. More recently, DLLs have found application in memory devices, such as SDRAM (synchronous dynanic access memory). In order to achieve sufficient coverage of frequency ranges and guarantee desired resolution, DLLs generally require long delay lines.
A diagram of a typical digital DLL is illustrated by FIG. 1. An input clock signal, CLKIN, is received via a buffer 10. The buffer 10 provides a buffered clock signal CKI and is coupled to a phase detector 12, a shift register 14, and a delay line 16. The delay line 16 is further coupled to a buffer 18 through which an output clock signal, CLKOUT, is produced. The CLKOUT signal is buffered through a buffer 20 to produce a feedback clock signal, CKF, to the phase detector 12. In operation, the phase detector 12 determines if a phase difference exists between the buffered input and feedback clock signals, CKI and CKF. The phase difference determines an appropriate shift in the buffered input clock signal via adjustment of the shift register 14 to select sufficient delay via the delay line 16, as is well understood by those skilled in the art.
While digital DLLs, such as that shown in FIG. 1, do provide clock deskew capabilities, several disadvantages result as clock speeds continue to increase. In order to achieve high resolution and coverage of wide frequency ranges, the delay cells in the delay line 16 and associated register cells in shift register 14 increase in number. For example, typically 20-30 serially coupled buffers for delay line 16 are needed for 200 MHz (megahertz) clock signals. The expansion in length of the delay line leads to larger silicon area requirements and higher power consumption. Other problems with increased delay line length include a longer lock-in time and larger high frequency signal distortion.
Attempts to combat the problems associated with increasing delay line lengths typically involve complicated circuitry, such as addition of additional delay lines and mixers, through analog circuitry. The additional circuitry results in greater complexity and thus greater expense, which is particularly detrimental for DRAM circuits. Therefore, a need exists for more elegant and cost effective solutions to reducing delay line length in DLLs.